Binary signaling is a popular scheme widely used in a serial data link; for instance, SATA (Serial Advanced Technology Attachment). In such a serial data link, a bit stream is transmitted at a certain nominal rate fs in accordance with a first clock signal; each bit within the bit stream represents either a logical “1” or a logical “0” (hereafter, “1” and “0”) datum; a “1” is represented by a voltage of a first level of a certain nominal duration Ts, where Ts=1/fs, while a “0” is represented by a voltage of a second level of the certain duration Ts; and as a result, the bit stream is represented by a voltage signal toggling back and forth between the first level and the second level in accordance with the bit stream to be transmitted. The voltage signal is received by a receiver via a channel (for instance, a cable). The channel usually disperses the voltage signal; the dispersion results in ISI (inter-symbol-interference), which needs to be corrected by the receiver in order to detect the bit stream accurately.
A functional block diagram of a receiver 100 of a serial data link is depicted in FIG. 1. Receiver 100 comprises: a linear equalizer 110 for receiving a dispersed signal and outputting an equalized signal; an ADC (analog-to-digital converter) 120 for receiving the equalized signal and outputting a digitized signal; and a DFE (decision feedback equalizer) 130 for receiving the digitized signal and outputting a recovered bit stream. The purpose of the linear equalizer 110 is to perform a preliminary equalization such that the ISI in the equalized signal is partly removed. There is, however, still some residual ISI that needs to be handled. DFE 130 effectively removes the residual ISI, so that the bit stream embedded in the digitized signal can be accurately detected. DFE 130 is a DSP (digital signal processing) circuit that processes the digitized signal generated by ADC 120. To accurately equalize the digitized signal, ADC 120 must have an adequate resolution. Prior art receivers usually demand ADC 120 to have at least 6-bits resolution for receiver 100 to work satisfactorily. For instance, for a serial data link of data rate of 10 Gb/s, a 6-bit ADC at a sampling frequency of 10 GHz is needed. It is very difficult to design such ADC. Therefore, receiver 100 is hard to implement for high speed serial data link.